DVD - Lecture 1d: The Chip Design Flow

Name: DVD - Lecture 1d: The Chip Design Flow
Uploaded: 2022-10-12T13:54:20.000Z
Duration: 36 min

Chip Design Flow

In this section, the speaker provides an overview of the chip design flow, outlining the steps involved in building a chip.

Definition and Planning

The process starts with definition and planning.

Marketing requirements document outlines what the chip should include and how it will be sold.

Chip architecture team defines buses, connectivity partitions, functionality, power, frequency, etc.

Design teams create sub-partitions and discuss board requirements and floor plan.

Design and Verification

RTL (Register Transfer Level) design is used to describe the chip's design using hardware description languages like Verilog or VHDL.

Intellectual Property (IP) blocks are integrated into the chip design.

Various checks such as linters, synthesisability checks, formal verification, and functional verification are performed on IP blocks.

Verification is done at unit level, subsystem level, and full-chip level to ensure coverage.

IP Integration

Two types of IPs: hard IP and soft IP.

Soft IP: RTL code that can be easily moved between processes but requires integration work.

Hard IP: Pre-existing layout provided by an IP provider designed for a specific process; difficult to migrate between processes but easier to integrate.

Process in Fab

Choosing a process for fabrication has a significant impact on chip performance and specifications.

Project kickoff marks the transfer of designs to implementation teams.

Design and Verification Stage

This section focuses on the design and verification stage of chip development.

RTL Design

RTL describes the chip's design using hardware description languages like Verilog or VHDL.

Intellectual Property (IP) blocks are integrated into the overall design.

Verification

Checks such as linters, synthesisability checks, formal verification, and functional verification are performed on IP blocks.

Verification is done at unit level, subsystem level, and full-chip level to ensure comprehensive coverage.

IP Integration

Two types of IPs: hard IP and soft IP.

Soft IP: RTL code that requires synthesis, placement, and routing; can be easily moved between processes.

Hard IP: Pre-existing layout provided by an IP provider; difficult to migrate between processes but easier to integrate.

Conclusion

The speaker concludes the lecture by summarizing the importance of process selection and the integration of intellectual property (IP) blocks in chip design.

Process Selection

Choosing the right fabrication process is crucial for achieving desired chip performance and specifications.

IP Integration

Integrating intellectual property (IP) blocks into the chip design is a critical step.

Two types of IPs: hard IP and soft IP, each with its own advantages and considerations.

FPGA Design and Verification

The transcript discusses the use of FPGAs in design and verification processes, as well as the emergence of hardware emulation for prototyping.

FPGA Design and Verification

With the increase in FPGA capacity, designs can be synthesized onto FPGAs for hardware speed verification.

Hardware emulation has emerged as another prototyping paradigm, using large boxes like Cadence Palladium to test gate-level designs at manageable speeds.

Logic synthesis is the process of converting a high-level behavioral model (RTL) into actual gates.

Inputs for logic synthesis include technology library files, RTL files, constraint files (SDC), and design-for-test definitions.

The output of logic synthesis is a gate-level netlist that describes the implementation of RTL using logic gates.

Technology mapping is performed to implement the logic netlist using available standard cell library gates.

Optimization processes are applied to meet timing, area, power constraints.

Various checks are conducted after synthesis, including gate-level simulation, logic equivalence verification, static timing analysis, power and area estimation.

Physical Implementation: Chip Design

This section covers physical implementation or back-end design where gate-level netlists are placed on a chip. It also discusses different aspects such as power distribution, clock tree synthesis, routing connections between logic gates and IPs.

Physical Implementation: Chip Design

Physical implementation involves placing gate-level netlists on a chip.

The chip includes landing pads for external connections and an I/O ring for interfacing with the outside world.

Power distribution is essential for providing VDD and ground rails throughout the chip.

Standard cells are placed in rows within the chip's core area.

Clock tree synthesis ensures proper clock signal distribution to flip-flops and other components that require a clock input.

Routing involves connecting different logic gates and IPs without violating design rules or causing shorts.

Verification steps include design rule checks, layout versus schematic checks, antenna checks, electromigration checks, and logic equivalence verification.

Post-layout simulations can be performed to evaluate chip performance with actual delays.

Foundry and IP Providers

This section discusses the role of foundries in providing device models and tech files for the chip manufacturing process. It also mentions the involvement of IP providers who supply standard cells, memory compilers, I/O buffers, and other hard IPs.

Foundry and IP Providers

The foundry provides device models that describe how transistors work.

Tech files describe the layers and parasitics involved in chip manufacturing.

Design rules specify how layouts should be created based on the provided layers.

IP providers offer standard cells, memory compilers (SRAMs/ROMs), I/O buffers, and hard IPs.

These components are essential for implementing various functionalities within the chip.

The transcript is already in English.

Back-End Flow Overview

This section provides an overview of the back-end flow in chip design.

RTL to Gate Level Conversion

Designers start with RTL (Register Transfer Level) code, such as Verilog or VHDL.

Constraints are defined in an SDC (Synopsys Design Constraints) file.

IP (Intellectual Property) blocks, like standard cells and macros, are provided by vendors.

Synthesis tool converts RTL code to gate-level representation.

Design for Test and Floor Planning

Automatic Test Pattern Generation tool is used for design-for-test purposes.

Floor plan determines the placement of different parts on the chip.

Placement algorithm places millions of gates based on the floor plan.

Clock Tree Synthesis and Routing

Clock definitions are provided based on the placement information.

Clock tree synthesis tool designs a low-skew clock network.

Router connects pins of cells and IPs according to design rules.

Post Layout Checks and Exporting

Various checks are performed, including static timing analysis, DRC (Design Rule Checking), LVS (Layout vs. Schematic), density checking, power analysis, etc.

Parasitic extraction takes into account signal integrity.

After routing and checks, layout description is exported as a GDs file for fabrication.

Conclusion and References

The lecture concludes with a list of terminology introduced and references mentioned.

Terminology Introduced

Various terms related to chip design flow were discussed throughout the lecture.

References

Special thanks to Near Sever for providing an overview of the back-end flow. Additional references will be provided in future lectures if not explicitly mentioned in each slide.