TCON and TMOD Registers of 8051 Microcontroller: Working and Functions for Timer and Counter
Understanding T-Mode and T-Con Resistors in 8051
Introduction to Timer and Counter Configuration
- The video introduces the concept of T-mode and T-con resistors in the context of the 8051 microcontroller, emphasizing their role in configuring timers and counters.
- It is explained that the 8051 has two 16-bit timers (T0 and T1), both functioning as up counters, counting clock pulses either from an internal or external source.
Functionality of Timers
- The timers are divided into higher (TH) and lower (TL) bytes: TH0/TL0 for Timer 0 and TH1/TL1 for Timer 1. This structure allows for detailed control over timer operations.
- When using internal clock pulses, these timers operate as timers; when external clock signals are provided, they function as counters.
Configuring T-Con Resistor
- To configure timer actions, it is necessary to set values in the T-con resistor, which is bit-addressable allowing individual bits to be manipulated.
- The video details how specific bits within the T-con resistor indicate timer overflow conditions (TF0 for Timer 0 and TF1 for Timer 1).
Understanding Timer Overflow
- A timer overflow occurs when a timer reaches its maximum value (FFFFh), at which point it resets to zero. This event sets the corresponding overflow bit to '1'.
- Upon overflow, an interrupt service routine (ISR) is triggered by the microcontroller, which automatically clears the overflow bit after handling.
Control Bits for Starting Timers
- TR0 and TR1 bits within the T-con resistor control whether each timer starts counting. Setting these bits initiates counting based on either internal or external clocks.
- To start a timer, programming instructions such as
SETBmust be used to set TR0 or TR1 accordingly; clearing these bits halts their operation.
Interrupt Handling with External Signals
- The video discusses additional interrupt-related bits (IE0/IE1), indicating external interrupts INT0/INT1. These bits become '1' upon receiving an interrupt signal.
- Each interrupt type can trigger specific ISRs; once handled, these interrupt flags are cleared back to '0', ensuring proper flow of program execution.
Understanding Timer and Interrupt Configuration
Negative Edge Trigger Interrupts
- A negative edge trigger interrupt is generated when a signal transitions from high to low. This indicates that the corresponding bit will be set to 1 during this transition.
- When the interrupt bit is 0, it signifies a level-triggered interrupt, indicating that the signal remains low.
T Mode Register Overview
- The T mode register is not bit-addressable and is crucial for configuring timers or counters in different operational modes.
- Timer 1 and Timer 0 are both configured with 4 bits; the CT (Counter/Timer) bit determines whether the timer functions as a counter (bit = 1) or as a timer (bit = 0).
Gate Control for Timers
- The gate terminal enables control of the timer/counter based on external signals. If the gate bit is set to 1, it allows initiation via external interrupts INT0 or INT1.
- When using INT0 for Timer 0 and INT1 for Timer 1, these interrupts serve as start signals rather than traditional interrupts.
Modes of Operation
- There are four operational modes defined by two mode control bits (M0 and M1):
- Mode 0: M0 = 0, M1 = 0
- Mode 1: M0 = 0, M1 = 1
- Mode 2: M0 = 1, M1 = 0
- Mode 3: M0 = 1, M1 = 1
Configuration of TCON and TMODE Registers
- The TCON register manages how to start timers and handle external interrupts. It includes automatic bits TF0 and TF1 which do not require user intervention.