Static Timing Analysis- I

Static Timing Analysis in VLSI Design

Introduction to Static Timing Analysis

• The lecture introduces static timing analysis (STA) as a crucial component of the VLSI design flow, emphasizing its role in ensuring circuit timing safety.

• The discussion will span four lectures, covering basic concepts, mechanics, advanced topics, and constraints related to STA.

Purpose of Static Timing Analysis

• The primary goal of STA is to confirm that the circuit remains in a valid state during each clock cycle.

• STA tools verify if the design can operate at specified frequencies by using constraints defined in Synopsys Design Constraints (SDC) format.

Key Functions of STA Tools

• STA does not determine a frequency for operation; instead, it ensures that designs are safe to run at given frequencies under worst-case scenarios.

• It checks setup and hold times for flip-flops, ensuring data signals do not change within forbidden windows around clock edges.

Methodology of Static Timing Analysis

• STA tools adopt a pessimistic view when analyzing circuits, potentially flagging unnecessary violations but never suppressing real ones.

• Unlike dynamic analysis methods that apply test vectors, STA focuses solely on worst-case behavior without testing actual input combinations.

Comparison with Simulation Techniques

• In contrast to simulation which requires test vectors and checks functionality against expected outputs, STA ignores functional correctness and only assesses timing arcs.

Understanding Static Timing Analysis and Synchronous Design

Purpose of Simulation in Circuit Design

• The primary goal of simulation is to verify the correct sequence of zeros and ones generated by a circuit, focusing on timing rather than functionality.

• In Static Timing Analysis (STA), analysis is conducted with a pessimistic view of delays and design attributes, contrasting with simulation that uses specified test vectors.

Characteristics of Synchronous Design

• A synchronous design typically includes flip-flops; for simplicity, ideal conditions are assumed where clock-to-Q delay, setup time, and hold time are all zero.

• Buffers exist in the data path (d1, d2, d3) and clock path (c1, c2), which introduce delays. Inputs at the port 'in' are represented as digital values (a, b, c, d).

Initial State Definition

• The initial state is defined by the output values at the Q pins of two flip-flops: FF1 has value p and FF2 has value q.

• The behavior of the circuit across different clock cycles will be analyzed based on various buffer delay scenarios.

Analyzing Buffer Delays

• If delays (d1, d2, d3) are finite but less than one clock period while c1 and c2 have negligible delays:

• Input sequences propagate through buffers leading to specific states at each clock cycle.

Valid States in Synchronous Circuits

• For valid states when delays are less than one clock period:

• Initial state: pq → subsequent states: ap → ba → cp. These represent how inputs affect outputs over time.

Potential Issues in Synchronous Circuits

• If delay for buffer d2 exceeds one clock period but remains under two:

Understanding Clocking Issues in Synchronous Circuits

Disruption of States in Flip-Flops

• The values at flip-flop FF2 will not be captured in the next clock cycle but rather in the subsequent one, leading to disrupted states (pq, aq, bp, ca).

• The circuit's states differ from expected synchronous states (ap, ba, cb), indicating a loss of synchronicity and resulting in invalid states due to late data arrival.

Zero Clocking Scenario

• This phenomenon is termed "zero clocking," where the clock fails to capture correct data due to timing issues.

• In this scenario, delays are negligible except for element c2 which has a positive delay (delta), causing incorrect data propagation.

Double Clocking Issue

• Data can be captured by two flip-flops during the same clock edge due to varying delays, leading to a state of double clocking.

• This results in invalid states as both flip-flops receive the same data simultaneously.

Mitigation Strategies with NSTA Tool

• The NSTA tool prevents zero clocking through setup analysis or late analysis by ensuring that data does not arrive too late at capture flip-flops.

• To avoid double clocking, hold analysis or early analysis is employed to ensure that data does not reach capture flip-flops too early.

Handling Multiple Flip-Flops and Timing Constraints

• In real designs with numerous flip-flops, timing constraints are checked pairwise between adjacent synchronously connected flip-flops.

• The tool accounts for various combinational gates along the path and adds their delays when checking timing requirements.

Non-Ideal Flip-Flop Considerations

Understanding Setup and Hold Time in Synchronous Circuits

Overview of Flip Flop Timing Analysis

• The verification process for synchronous circuits considers both setup time and hold time constraints of flip flops, ensuring that the states are valid.

• Static Timing Analysis (STA) tools check that data from the launch flip flop is reliably captured by the capture flip flop in subsequent clock cycles while verifying setup requirements at the capture side.

Circuit Configuration and Delay Elements

• In a typical circuit configuration, there are two adjacent flip flops with a combinational element between them. The delays associated with these elements include T_launch and T_capture for clock paths.

• Timing checks focus on the capture flip flop rather than the launch flip flop, emphasizing that setup and hold time validations occur at the capture side.

Arrival Time Calculation

• When analyzing arrival times, it is assumed that a clock edge occurs at t = 0. The signal undergoes various delays before reaching its destination.

• The arrival time at the D input of the capture flip flop can be calculated as T_launch + T_clock_to_q_delay + T_data.

Required Time for Data Settlement

• Data must settle before a specified duration known as T_setup to ensure reliable capturing by the next clock edge. This timing constraint is critical for proper circuit operation.

• The next clock edge occurs after one complete clock period (T_period), necessitating that data arrives before this point minus any required setup time.

Establishing Timing Constraints

• A key constraint can be expressed as T_required_setup > T_arrival, indicating that arrival times must meet or precede required times to maintain circuit integrity.

• By rearranging terms, we derive an equation linking clock period with other timing parameters: T_period + T_capture - T_setup > T_launch + T_clock_to_q_delay + T_data.

Clock Skew Considerations

• Clock skew (denoted as Delta L_c) represents differences in signal arrival times across different points in a circuit. It plays a crucial role in determining minimum clock periods necessary for valid operations.

Understanding Flip-Flop Timing Constraints

Path Attributes and Delay Computation

• The attributes of the flip-flop clock, including clock-to-Q delay and setup time, are derived from technology lab rates. T_data will be computed based on the sum of delays encountered for each gate in the path.

Variability in Timing Parameters

• Clock-to-Q delay, setup time, and signal skew can vary due to process-induced variations. Multiple paths between Q and D exist, necessitating consideration of maximum values for worst-case scenarios.

Maximum Delay Considerations

• In cases with multiple paths (e.g., delays of 100, 200, and 150), the maximum delay should be selected (200) to ensure constraints are not violated. This approach helps prevent failures in timing constraints.

Impact of Clock Frequency on Setup Violations

• Decreasing clock periods increases frequency but risks violating timing constraints. There is a limit beyond which designs cannot function reliably without failure.

Ideal Flip-Flops Scenario

• If ideal flip-flops are considered (with zero clock-to-Q delay and setup time), the constraint simplifies to T_period > T_data_max. This indicates that no zero clocking occurs if delays remain under one cycle.

Hold Requirements in Flip-Flops

Understanding Hold Time Constraints

• The hold requirement checks that data launched by a flip-flop does not get captured by another flip-flop during the same clock cycle, ensuring stability within that period.

Arrival Time Calculation

• The arrival time at a capture flip-flop includes launch time plus any additional data path delays. Required times must account for both capture time and hold requirements.

Importance of Hold Time Duration

Understanding Hold Time Violations in Flip-Flops

Overview of Hold Time Constraints

• The discussion begins with the importance of timing windows for data arrival, emphasizing that data must not arrive too early to avoid hold violations.

• It is crucial that the arrival time of data exceeds the required hold time, ensuring that data can come at any point after this threshold.

• The analysis expands on inequalities related to flip-flop pairs, focusing on the relationship between launch and capture times and their impact on hold requirements.

Factors Influencing Hold Time Violations

• The likelihood of a hold violation increases as certain parameters decrease; thus, minimum delays should be considered for pessimistic analysis.

• A decrease in either the data path delay or launch clock path delay heightens the risk of violating hold time constraints.

Ideal Flip-Flop Conditions

• For an ideal flip-flop scenario, both clock-to-Q delay and hold time are zero, leading to a simplified constraint: delta Lc + t_data_min > 0.

• While t_data_min cannot be negative, delta Lc can become negative if capture delays exceed launch delays.

Implications of Clock Variability

• The discussion highlights how ideal conditions assume negligible clock-to-Q delays; however, real designs may encounter double clocking scenarios due to these variations.

• During logic synthesis, assuming a zero clock-to-Q delay often leads to more favorable outcomes regarding meeting hold time constraints.

Timing Analysis in Design Phases

• Shift register configurations pose higher risks for hold violations due to direct connections between flip-flops without intervening logic.

• Logic synthesis typically does not prioritize hold checks since they depend heavily on accurate clock tree synthesis results obtained later in physical design stages.

Summary of Key Takeaways

• Most hold violations identified during logic synthesis are likely resolved through wire delays introduced later in design phases.

Understanding Clocking in Circuit Design

Setup and Hold Time Requirements

• Discussion on the concepts of zero clocking and double clocking within circuit design, emphasizing their significance in timing analysis.

• Examination of how setup constraints are derived for circuits, ensuring that they meet necessary timing requirements.

• Explanation of hold time requirements for flip-flops, highlighting their critical role in maintaining data integrity during transitions.

• Overview of the relationship between setup/hold times and overall circuit performance, stressing the importance of meeting these criteria.