VIDEO
HIGHLIGHT
Log InSign up
DVD - Lecture 2d: Verilog FSM Implementation
SummaryTranscriptChat

DVD - Lecture 2d: Verilog FSM Implementation

Introduction to Verilog State Machines

In this section, the speaker introduces the concept of writing state machines in Verilog and provides an example of a 4-bit counter.

Writing a State Machine in Verilog

  • A state machine can be written in Verilog with a one-to-one mapping between the state machine and the code.
  • The example provided is a 4-bit counter with inputs for clock, reset, activate signal, and up/down count. It has two output signals for count and overflow.
  • The size of the counter is parametrizable using a default value of 4 bits.
  • The state machine has four states - idle, count up, countdown, and overflow - which are enumerated for clarity.

Encoding the State Machine into Verilog

  • The different states are represented using a two-bit vector that is enumerated with meaningful names.
  • The next state logic is implemented using case statements that check the current state and input signals to determine the next state.
  • The output logic is implemented using combinational logic that checks the current state and input signals to determine the output values for count and overflow.

One Hot Encoding

In this section, the speaker discusses the use of one hot encoding in their code to make it more readable.

One Hot Encoding

  • The speaker explains that they decided on using one hot encoding for each state.
  • They explain that for each state, a bit is needed and they called idle 0001, count up 0010, countdown 0100 and overflow 1000.
  • The speaker notes that these words will be used in their code to make it more readable.

Writing the Combinational Block

In this section, the speaker discusses writing the combinational block and how it computes what the next state of the system should be.

Combinational Block

  • The speaker explains that they declared two registers State and Next State both of them were four bits because they have four states that are one hot encoded.
  • They explain that they will now have completely combinational logic that will compute what the next state of their system should be once the clock rises.
  • The speaker notes that they will use always at Star and actually don't care what's in the sensitivity list because this star will decide by itself.
  • They start with a case statement to determine what current state is.

Case Statement

In this section, the speaker discusses how to write a case statement to determine what current state is.

Writing a Case Statement

  • The speaker explains that they start with a case statement to determine what current state is.
  • Depending on which state is determined from the case statement different things happen which describe our state machine.

Idle State Description

In this section, the speaker describes the idle state and what happens when Act is zero or one.

Idle State

  • The speaker notes that if Act is zero, they will stay in idle.
  • If Act is one, depending on up down they will either go to count up or countdown.
  • They explain that if up down is high then they will be counting up and the next state is count up state else the next state is countdown state.

Count Up State Description

In this section, the speaker describes the count-up state and what happens when act goes to zero or stays at one.

Count Up State

  • The speaker explains that when act goes to zero, they will go back to idle.
  • When act stays at one and up down stays at one while staying count up.
  • When act stays at one but countdown goes down they'll go to countdown.
  • They note that there's an overflow condition where if there's a situation where we have let's say we're a four-bit counter if it's 1111 and we want to go up our next state will be an overflow.

Overflow Condition

In this section, the speaker discusses how to handle overflow conditions in their code.

Overflow Condition

  • The speaker explains that for overflow conditions they take 11000001 which would be a whole bunch more zeros if we had a longer counter width than four and then shift it left by counter width so we get the number 10000 which works for any bit width.
  • They note that their condition over here to get into the overflow state is if count equals 1 shifted left by counter with minus 1.

Countdown State Description

In this section, the speaker describes the countdown state and how it differs from the count-up state.

Countdown State

  • The speaker notes that the description of countdown is exactly the same as count up just with different conditions.
  • They explain that if count is zero then the next state is overflow else the next state is countdown.

Overflow State Description

In this section, the speaker describes what happens in their code when they reach an overflow state.

Overflow State

  • The speaker explains that in their overflow state they want to stay.

State Machine Design

In this section, the speaker explains how to move between states in a state machine using sequential and combinational logic. They also discuss synchronous and asynchronous resets.

Moving Between States

  • The next state is determined by combinational logic.
  • A sequential block is used to move between states.
  • The sequential block uses a non-blocking assignment.
  • Every time the clock goes high, the state moves to the next state.

Synchronous Resets

  • A count signal is used for synchronous resets.
  • The counter increments or decrements depending on the current state.
  • An asynchronous reset puts the counter back at zero.

Overflow Signal

  • An overflow signal is dependent only on the state and not on the clock.
  • Output assign overflow equals if State equals overflow then output a one else output is zero.

Test Bench for State Machine

In this section, the speaker explains how to write a test bench for a state machine.

Test Bench Setup

  • Instantiate a 5-bit counter instead of a 4-bit counter.
  • Use regs for input signals and wires for output signals.
  • Instantiate the module with dot notation that connects all signals to ports of module.

Simulation Setup

  • Initialize different values such as starting clock high, reset low, activate low, and up down high.
  • Monitor different signals with system tasks that print out on screen.
  • Delay simulation by 100 time units before releasing reset by raising it to one.

Stimuli

At time step 100:

  • Raise activate signal
  • Start counting up until we hit overflow

Testing a Design

In this section, the speaker discusses how to test a design using a simulator. They explain how they reset and activate their design and then test it using a directed test.

Steps for Testing a Design

  • Run the code in a simulator.
  • Reset the design after 100 time units.
  • Activate the design and start counting.
  • Test all signals and states in the state machine using a directed test.

The Intel 8088 Microprocessor

In this section, the speaker talks about the Intel 8088 microprocessor, which was used in IBM's personal computer. They discuss its architecture, specifications, and why it became so successful.

Key Points

  • The Intel 8088 microprocessor was used in IBM's personal computer.
  • It had 29,000 transistors and ran at a frequency of 10 MHz.
  • It had an x86 architecture with an 8-bit output bus.
  • The x86 architecture is still used today in Intel and AMD machines.
  • The IBM PC was based on this chip, making it one of the best-selling computers of all time.

Personal Story About the Intel 8088 Microprocessor

In this section, the speaker shares a personal story about the Intel 8088 microprocessor and how it was designed.

Key Points

  • The speaker knows the guy who designed the Intel 8088 microprocessor.
  • The designer wrote his name on the chip in Hebrew, which management didn't notice.
  • The 8088 was not as good a chip as the earlier 8086, but it was successful because it was cheaper to produce.
  • IBM selected this chip for their personal computer, making it one of the best-selling computers of all time.
Playlists: Digital VLSI Design (RTL to GDS)
Video description

Bar-Ilan University 83-612: Digital VLSI Design This is Lecture 2 of the Digital VLSI Design course at Bar-Ilan University. In this course, I cover the basics of Chip Implementation, from designing the logic (RTL) to providing a layout ready for fabrication (GDS). Lecture 2 overviews the Verilog Hardware Description Language and provides coding style guidelines for writing synthesizable register transfer level (RTL) code. Lecture 2d shows how to implement a basic finite state machine in Verilog according to synthesizeable coding style. Lecture slides can be found on the EnICS Labs web site at: https://enicslabs.com/academic-courses/dvd-english/ All rights reserved: Prof. Adam Teman Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs Faculty of Engineering, Bar-Ilan University