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DVD - Lecture 1c: Design Automation
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DVD - Lecture 1c: Design Automation

Design Automation

This section discusses the evolution of design automation, from manual processes to the use of various tools for different levels of design automation.

Evolution of Design Automation

  • In the early days, chip designs were done by hand on paper, but as the complexity increased, computer-aided design (CAD) tools were introduced.
  • Mainframe CAD systems and digitizers were used to input coordinates into the system.
  • Millimeter paper was used for hand-drawn gate layouts.
  • Tape out, which refers to sending design files to fabrication plants, originally involved recording data onto cassettes or even taping plots together on a basketball court.
  • Today, design automation relies on a range of tools for different stages:
  • High-level synthesis and logic synthesis tools for RTL and system-level designs.
  • Schematic capture tools for designing transistors layout.
  • Layout tools for PCB design.
  • Simulation tools using compact models for transistor-level simulations.
  • Logic simulation tools based on Boolean equivalence of logic gates.
  • Hardware emulation for testing designs before fabrication.
  • Technology CAD and field solvers for device-level analysis and design.
  • Analysis and verification tools including functional verification, formal verification, equivalence checking, static timing analysis, physical verification (DRC/LVS), validation (ATPG/BIST), and mass preparation (OPC).
  • The Cadence flow is commonly used in this course with RTL designed in Verilog.

Summary

In this transcript segment about design automation:

  • The evolution from manual chip designs to computer-aided design (CAD) tools was discussed.
  • Different levels of design automation were explained along with the corresponding tools used at each stage.
Playlists: Digital VLSI Design (RTL to GDS)
Video description

Bar-Ilan University 83-612: Digital VLSI Design This is Lecture 1 of the Digital VLSI Design course at Bar-Ilan University. In this course, I cover the basics of Chip Implementation, from designing the logic (RTL) to providing a layout ready for fabrication (GDS). Lecture 1 covers the motivation for the course and an introduction to the chip design process. Part 1c goes over the concept of design automation and how it enables us to build complex ICs. Lecture slides can be found on the EnICS Labs web site at: https://enicslabs.com/academic-courses/dvd-english/ All rights reserved: Prof. Adam Teman Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs Faculty of Engineering, Bar-Ilan University