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DVD - Lecture 2a: Verilog
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DVD - Lecture 2a: Verilog

Introduction to Verilog Hardware Description Language

In this section, the instructor introduces the Verilog hardware description language (HDL) and explains its significance in digital VLSI design. The differences between HDLs and sequential programming languages are highlighted, emphasizing the parallel execution of hardware constructs in Verilog.

What is a Hardware Description Language?

  • A hardware description language (HDL) is not just any other programming language.
  • HDLs are used to describe actual hardware constructs that execute in parallel, unlike sequential programming languages.
  • Code ordering is flexible in HDLs, allowing for different sequences of execution.
  • Execution of code is triggered by events, which cause changes in signals or variables.

Coding Styles in Verilog

  • Verilog has three coding styles or abstraction levels: structural code, RTL (register transfer level), and behavioral code.
  • Structural code represents a low-level description of gates and their connectivity but lacks readability.
  • RTL is used to write synthesizable Verilog that can be converted into gate-level netlists. It provides a more readable and behavioral level of description.
  • Behavioral code allows for higher-level constructs but cannot be automatically converted into hardware.

Importance of Coding Style

  • Due to parallel execution and event-driven simulation, coding style becomes crucial to ensure predictable behavior.
  • Different simulators may yield different results if coding style is not followed consistently.
  • A specific coding style will be taught to write Verilog that works reliably.

Three Abstraction Levels in Verilog

This section discusses the three abstraction levels available in Verilog - structural code, RTL, and behavioral code. Each level serves a specific purpose in describing the device under test (DUT) or system being modeled.

Structural Code

  • Structural code represents the lowest level of abstraction in Verilog.
  • It consists of a list of gates and their connectivity, without providing much readability or understanding.
  • Structural code is used to describe the DUT, including gates, transistors, and interconnections.

RTL (Register Transfer Level)

  • RTL is a higher-level abstraction level that allows for more readable and behavioral descriptions.
  • It is used to write synthesizable Verilog that can be converted into gate-level netlists.
  • RTL describes the flow of data transfers between registers and operations performed on them.

Behavioral Code

  • Behavioral code represents the highest level of abstraction in Verilog.
  • It allows for writing test benches and describing system behavior using programming constructs like loops.
  • However, behavioral code cannot be automatically converted into hardware.

Conclusion

The lecture introduces the Verilog hardware description language (HDL) and explains its significance in digital VLSI design. The differences between HDLs and sequential programming languages are highlighted, emphasizing the parallel execution of hardware constructs in Verilog. Three coding styles or abstraction levels - structural code, RTL, and behavioral code - are discussed, each serving a specific purpose in describing the device under test (DUT) or system being modeled. Following a consistent coding style becomes crucial to ensure predictable behavior in event-driven simulations.

Playlists: Digital VLSI Design (RTL to GDS)
Video description

Bar-Ilan University 83-612: Digital VLSI Design This is Lecture 2 of the Digital VLSI Design course at Bar-Ilan University. In this course, I cover the basics of Chip Implementation, from designing the logic (RTL) to providing a layout ready for fabrication (GDS). Lecture 2 overviews the Verilog Hardware Description Language and provides coding style guidelines for writing synthesizable register transfer level (RTL) code. Lecture 2a presents the motivation for Hardware Description languages and introduces Verilog. Lecture slides can be found on the EnICS Labs web site at: https://enicslabs.com/academic-courses/dvd-english/ All rights reserved: Dr. Adam Teman Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs Faculty of Engineering, Bar-Ilan University