Digital Design (120 8a3) Propagation Delays 1 (gate-level circuits)

Understanding Delay in Logic Gates

In this video, we will learn about the delays within physical logic gates and how to compute the total delay through a series of gates. We will also explore the causes of delay through each gate.

Propagation Delays in Logic Gates

• Every gate and wire has a propagation delay.

• Gates placed in sequence lead to compounding propagation delays.

• To guarantee correct values, we must read them after enough time has elapsed since the inputs changed.

• The incoming rise time and internal fall time cause delay through each gate.

• Two symbols are defined for propagation times: tPHL and tPLH.

Estimating Total Propagation Delay

• There are several complications that lead us to make assumptions when estimating total propagation delay in a circuit.

• Assumptions include assuming tPLH is equal to tPHL, all inputs have the same effect, fanout has no impact, and longer wires have no impact.

Computing Overall Propagation Delay

• Our goal is to compute the overall propagation delay of a full adder logic circuit.

• We will use a timing diagram to work our way through the circuit from left-to-right.

Computing Total Propagation Delay

In this section, we will continue our analysis of the full adder logic circuit by computing its total propagation delay.

Timing Diagram Analysis

• The input signals change at time 20 ns.

• We work our way through the circuit from left-to-right using the timing diagram.

• We add up the propagation delays of each gate to get the total propagation delay of the circuit.

Results

• The total propagation delay of the full adder logic circuit is 28 ns.

Understanding Propagation Delays in Digital Circuits

This video explains how to understand propagation delays in digital circuits using a full adder circuit as an example. The video demonstrates how to use timing diagrams and compounding delays over the top of the circuit diagram.

Full Adder Circuit

• A full adder circuit is used as an example to explain propagation delays in digital circuits.

• The output of the exclusive-Or gate changes after a delay when one of its inputs drops low.

• The output of the And gate changes after a delay when one of its inputs drops low.

• Signal z is low at first because at least one input is low for the first half of the timing diagram, then it jumps high after both inputs are high.

• Signal S starts low and jumps high 20 ns later when Cin jumps high. It also jumps high again 20 ns later when x jumps high causing Cin to drop low.

• Signal Cout starts and ends at the same value with a temporary blip in between due to values changing within the circuit before settling on its final value after z settles on its final value plus a 15 ns delay.

Propagation Delay Calculation

• Compounding delays over the top of the circuit diagram can be used as a quicker way to calculate propagation delays than using timing diagrams.

• Starting from 0 ns, for every gate encountered, add the gate delay to the largest input delay until reaching each output signal's final value delay time which should be waited before reading any output values from that signal.

• The overall propagation delay is the larger of the output signal delays, which in this case is 45 ns.