8 Memory Technologies

Review of Computer Architecture

In this section, the instructor reviews computer architecture and its importance as a prerequisite for the course. The focus is on understanding memory technology and cache design.

Memory Technology and Caches

• Memory technology is discussed as a motivation for caches. Different types of memory technologies such as DRAM and SRAM are explained.

• The need for caches is motivated by the limited information storage capacity of processors. Caches store a subset of information to improve performance.

• Classification of caches is introduced, including associativity, size, and multiple things that can fit in one set.

• A brief introduction to cache performance is provided.

Memory Technology: Register File

• A naive flip-flop based register file is presented as a conceptual idea of memory storage.

• The challenges with building large register files are discussed, including aspect ratio issues and wire propagation delays.

Memory Arrays: Register File Array

• The transition from a naive register file to a memory array is explained.

• Analog circuits are used to connect bits to respective buses in the memory array.

• The decode process involves word lines that turn on specific wires based on the address.

This summary covers the first part of the transcript up until timestamp 415s.

New Section

This section discusses the concept of multiplexors and the use of address subsets in circuit design.

Multiplexor and Address Subset

• A multiplexor is used to combine multiple bits into a single output.

• In this example, a 4-bit wide readout or write is used with 8 bits across.

• The address is split into subsets for word creation and column decode.

New Section

This section explains the need for a 2:1 column decode in larger arrays and introduces the circuit level diagram of a register file.

Column Decode and Register File

• Larger arrays require a 2:1 column decode.

• The circuit level diagram of a register file consists of two cross-coupled inverters.

• Read bit lines are connected to the output of the inverters using pass gates.

• Write bit lines are connected when the write word line is activated.

New Section

This section delves into the functioning of read and write operations in register files.

Read and Write Operations

• When the read word line is energized, it connects the output of an inverter to the read bit line for reading data.

• For writing data, the write word line is activated, connecting both Q and Qbar to the write bit line.

• To flip data from 0 to 1 or vice versa during writing, the right bit line is overpowered by grounding it stronger than what either inverter can drive.

New Section

This section compares register files with memory arrays (SRAM) in terms of their structure and usage.

Memory Arrays (SRAM)

• Memory arrays like SRAM are used for storing larger amounts of data, such as caches.

• SRAM cells have two sets of bit lines: bit and bit bar.

• Cross-coupled inverters are used in the middle of the cell.

• Sense amps are added to sense small differences between bit and bit bar for reading data.

New Section

This section highlights the difference between register files and SRAM in terms of their design and usage.

Register Files vs. SRAM

• Register files are often multi-ported, while SRAM arrays reuse the same bit lines for both read and write operations.

• Register files prioritize speed and multiple ports, while SRAM is more dense in storage capacity.

New Section

This section introduces dynamic random-access memory (DRAM) and its structure.

Dynamic Random-Access Memory (DRAM)

• DRAM is a type of memory commonly found in computers.

• Each DRAM cell consists of one transistor connected to a capacitor that stores charge.

• The capacitor is built using deep trenches with two metal plates separated by a dielectric material.

New Section

This section explains how capacitors are constructed in DRAM cells.

Construction of Capacitors

• Capacitors in DRAM cells are built using long and narrow trenches to maximize storage density.

• Two metal plates are placed inside the trench with a dielectric material between them.

New Section

This section discusses the connection between transistors, capacitors, and bit lines in DRAM cells.

Transistors and Bit Lines

• Transistors connect the capacitor, which has an unusual shape due to its tall aspect ratio, to the bit line.

Building on Standard CMOS Process

The speaker discusses the challenges of building on a standard CMOS process and the need for a specialized DRAM manufacturing process.

Challenges of Building on Standard CMOS Process

• It is typically difficult to build on a standard CMOS process.

• Specialized DRAM manufacturing processes are required.

• Mixing different technologies can result in larger cell sizes.

Advantages of DRAM

• DRAM allows for larger amounts of storage in a smaller area compared to SRAM.

• Each bit cell in DRAM consists of one transistor and one capacitor, making it more space-efficient.

How DRAM Works

• Data is stored by charging or discharging the capacitor connected to the bit line.

• Capacitors in DRAM cells store small amounts of charge, requiring sensitive circuitry for reading out data.

Challenges with DRAM

• Capacitors in DRAM cells may slowly lose their charge over time, requiring periodic refresh operations.

• Refreshing is necessary as modern-day computer memory holds data for only a few seconds or milliseconds.

Size Comparison: SRAM vs. DRAM

The speaker compares the sizes of SRAM and different types of DRAM cells, highlighting the advantages of optimized memory-specific processes.

Size Comparison: SRAM vs. Memory-Specific DRAM

• An SRAM cell built on a logic process is larger and consists of six transistors.

• A memory-specific DRAM cell is significantly smaller, consisting of only one transistor and one capacitor.

• Memory-specific processes allow optimization in the Z dimension, resulting in even smaller cell sizes.

Other Types of Cells

• A Damm built on an ASIC process with local interconnect has a slightly smaller size than an SRAM cell.

• Local interconnect utilizes poly silicon layer for interconnections, increasing density.

• A fully complementary logic cell built out of gates is even smaller than the previous cells.

• Custom logic cells are crucial for reducing RAM size and increasing memory capacity.

Trade-offs in Memory Technology

The speaker discusses the trade-offs involved in choosing different memory technologies based on factors like speed, capacity, latency, and bandwidth.

Trade-offs in Memory Technology

• Different memory technologies offer varying trade-offs between speed, capacity, latency, and bandwidth.

• Fast and small components like latches and registers provide low latency and high bandwidth.

• As memory size increases, access time becomes longer while capacity increases.

• Small components have low capacity but offer high bandwidth.

Considerations for Memory System Design

• Choosing the appropriate technology depends on where it fits within the overall memory system design.

• Trade-offs must be made based on specific requirements and priorities.