L3 4 Lenguaje máquina de un computador Code 2

Understanding Machine Language of Code 2

Introduction to Machine Language

• The lesson focuses on the machine language of the Code 2 processor, which serves as a model for understanding computer operation.

• Key topics include accessible elements from machine language, instruction and data formats, and the repertoire of machine instructions.

Elements Accessible from Machine Language

• The word length of Code 2 is 16 bits; all registers, memory words, and I/O ports operate with this bit length.

• There are 16 general-purpose registers (r0 to rf), an arithmetic logic unit (ALU) capable of addition, subtraction, logical operations, and bit shifts.

• Status flags include zero, sign, carry, and overflow indicators that activate based on ALU operations.

• Memory capacity is 64k words (128kb total), with addresses ranging from 00 to ff in hexadecimal notation.

• There are also 256 input ports (ip00 to ipff) and output ports (op00 to opff), where "ip" stands for input port and "op" for output port.

Data Formats in Machine Language

• Data representation uses signed integers in two's complement format; the leftmost bit indicates the sign (0 for positive, 1 for negative).

• Each instruction occupies 16 bits; the first four bits represent the opcode specifying the operation performed by that instruction.

Instruction Formats

• Five instruction formats exist:

• Format F0: Opcode only; remaining bits are unused.

• Format F1: Opcode followed by one register; other bits unused.

• Format F2: Opcode followed by a condition code; remaining bits unused.

• Format F3: Opcode followed by one register and an immediate value or literal data.

• Format F4: Opcode followed by a destination register and two source registers.

Example Instruction Breakdown

• An example given is an addition instruction (adds), which sums contents from two source registers into a destination register.

• Source registers are denoted as RS and RA while RX represents the destination register.

• The binary opcode for adds is 0110, corresponding to decimal 6, utilizing Format F4.

• In coding this instruction in binary:

• Bits = opcode,

• Bits = RX,

• Bits = RS,

• Bits = RA.

Understanding Machine Instructions and Memory Access

Instruction Encoding and Operation

• The instruction to add R1 and R8, storing the result in R9, is encoded as 6918 in decimal. This encoding can be derived from the mnemonic for the add instruction.

• The first six machine instructions facilitate data transfer between memory and registers, including loading data into registers and storing data back to memory.

Types of Instructions

• The initial instructions include:

• Moving data from memory to a register.

• Storing a register's content back to memory.

• Initializing register values.

• Input operations (from an input port to a register).

• Output operations (from a register to an output port).

• Following these are arithmetic logical instructions that allow for operations like addition, subtraction, shifts left/right, etc., along with control instructions for jumps and routine calls.

Execution Time Calculation

• Each instruction consumes a specific number of cycles; knowing this allows us to calculate execution time by multiplying cycles by the clock period (inverse of frequency).

Memory Access Instructions

• Memory access involves two main types: load (LD) which brings data from memory into registers, and store (ST) which sends data from registers back to memory.

• The effective address for both load and store is calculated using the formula Rd + V, where Rd is any register (R0-RF), and V represents an offset specified in the instruction.

Examples of Load/Store Operations

• For example, using LD r4 BB, if Rd = 0, it translates into binary operation code DLD with corresponding values indicating where data should be loaded from.

• Another example includes ST storage 7A, which stores the content of RF at memory address 007A. Here again, effective addressing follows Rd + V logic.

Addressing Modes

• When using indexed addressing mode with constant V while varying Rd (e.g., RD = 0x00, 0x01,...), it generates sequential addresses based on increments of V added to RD's value.

Immediate Load Instructions in Computer Architecture

Overview of Immediate Load Instructions

• The immediate load instructions are categorized into two types: low immediate load and high immediate load. The low immediate load sets the most significant 8 bits of a specified register to zero while loading the least significant bits with a specified value V .

• The operation code for the low immediate instruction is 0010 (2 in decimal), using format F3, which includes the operation code, target register, and value V .

High Immediate Load Instruction

• The high immediate load instruction replaces the most significant 8 bits of a specified register with the value from field V , leaving the least significant bits unchanged. Its mnemonic is lhi, with an operation code of 0011 (3 in decimal).

• For example, executing lli r7 ff sets the most significant 8 bits to zero and updates the least significant 8 bits to ff. In binary, this translates to setting specific bit values based on provided instructions.

Data Transfer Instructions

Input Operation

• Input operations transfer data from an input port to a designated register. The mnemonic used is in, requiring parameters for both the target register and input port.

• The operation code for input is represented as binary values 4 and 5. Format F3 specifies where data will be stored.

Output Operation

• Output operations move data from a register to an output port using the mnemonic out, specifying both source register and destination port.

• An example includes transferring content from register R5 to output port 01, represented in machine code as appropriate operation codes.

Arithmetic Logic Instructions

Basic Operations

• Arithmetic logic instructions include addition, subtraction, and NAND operations. Each has its own mnemonic and corresponding operation codes.

• A reference table illustrates arithmetic addition, subtraction, and NAND logic operations; NAND being unique as it complements logical AND results.

Examples of Arithmetic Operations

• For instance, executing an addition instruction like ads r2 ra rb sums contents of registers RA and RB into R2.

• Subtraction can also be performed similarly by subtracting contents between registers RA and RB.

Logical Operations Insights

Understanding NAND Logic

• Performing a NAND operation between two registers always yields one unless both inputs are one; thus producing zeros only when both inputs are true.

Practical Applications

• Comments on practical applications include using NAND for bitwise complement or doubling values through self-addition within registers.

Shift Operations and Control Instructions

Shift Operations: Left and Right

• The left shift operation moves all bits one position to the left, storing the most significant bit in a carry register and inserting a zero in the least significant position.

• The right shift operation shifts all bits to the right, with the least significant bit stored in the carry register. A zero is inserted as the most significant bit. An arithmetic right shift replicates the most significant bit instead of inserting a zero.

• Mnemonics for these operations include shl (shift left), shr (shift right), and shra (arithmetic shift right).

• Example: If register R7 contains certain data, performing a left shift will result in moving all bits leftward, with zeros filling in from the right.

• In an arithmetic right shift example using R7, bits are shifted to the right while maintaining the sign by replicating the most significant bit.

Control Instructions: Jumping and Calling Subroutines

Jump Instructions

• Jump instructions allow execution of code at addresses specified in register Rd. Before executing a jump, Rd must contain this address.

• There are five types of jump instructions:

• Unconditional jump

• Conditional jumps based on ALU results being zero or negative

• Jump if there was a carry

• Jump if overflow occurred

• Mnemonics for these jumps include br, bz, bsbc, and bv. The instruction format is F2 where first four bits represent opcode and next four represent condition codes.

Examples of Jump Instructions

• For instance, jumping to memory location 73B requires loading Rd with that address using immediate load instructions before executing an unconditional jump.

• Another example involves jumping to memory location 00A2 if an overflow occurs; this can be done with a single immediate load instruction followed by a conditional jump.

Subroutine Calls

• Call instructions initiate subroutines starting at addresses contained in Rd. Similar to jumps, Rd must hold this address prior to execution.

• After completing a subroutine, control returns via a return instruction. The stack pointer concept is crucial here for managing calls effectively.

How to Manage Stack Pointer Before Subroutine Calls

Setting Up the Stack Pointer

• To act as a stack pointer before making the first subroutine call, load the address of the stack header into register R. This address is typically a high memory address (e.g., FFF).

• The stack fills towards lower memory addresses, so precautions must be taken to ensure it does not overlap with program or data areas. For this, set R to FFFF.

Calling a Subroutine

• When calling a subroutine starting at address 00F0, if the last ALU operation results in zero, use instruction CZ (call if Z is 0).

• Load register Rd with the subroutine's address (00F0) using an immediate load instruction followed by executing the call.

Returning from Subroutines

• Each subroutine must end with a return instruction (RET). This returns control to the next instruction following the call.

• The return instruction has format F0, utilizing only its operation code; other bits can vary since they are ignored by control units.

Stopping Program Execution

• The stop instruction halts program execution and enters a wait state. This process involves two phases: fetching and executing instructions iteratively.

• Programs should conclude with a halt instruction unless in an indefinite loop. The mnemonic for halt is HALT, which has operation code F.

Summary of Instruction Set Architecture

• Code2 operates on 16-bit words across all registers, ALU operations, memory positions, and I/O ports. Its instructions follow a regular format using four most significant bits for operation codes.

• There are 16 distinct instructions available due to this structure. Six instructions facilitate data transfer between memory and registers or initialize general-purpose registers.

Types of Instructions

• Input/output instructions allow data transfer between ports and registers. Additionally, there are six arithmetic logical operations including addition, subtraction, logical AND, and bit shifts.

Control Instructions