LECTURE 12 : CMOS inverter basics

Introduction to Electronic Systems Design

Overview of Printed Circuit Boards (PCBs)

• The lecture begins with a discussion on printed circuit boards (PCBs), which are essential for creating complete electronic systems.

• Interconnecting wires, or tracks, are laid down on the PCB or other substrates like Rogers or silicon, depending on application requirements.

Understanding CMOS Inverters

• The focus shifts to electronic circuits, specifically inverters, with an emphasis on CMOS inverters (Complementary Metal-Oxide-Semiconductor).

• A CMOS inverter utilizes both PMOS and NMOS devices that complement each other in function.

Importance of Studying CMOS Inverters

• CMOS inverters are fundamental components found in nearly all integrated circuits (ICs), making their study crucial.

• Analysis performed on CMOS inverters can be extended to more complex circuits such as NAND and NOR gates.

Key Parameters of CMOS Inverter Performance

Cost Considerations

• Cost is evaluated not just financially but also in terms of area occupied by the circuit on silicon or PCB.

Robustness and Reliability

• Robustness is assessed through steady-state leakage current, which impacts the reliability and power consumption of the system.

Performance Metrics

• Performance is measured by how quickly the inverter can switch states; faster switching allows for higher operational frequencies.

Energy Efficiency

• Energy efficiency is critical as many electronic systems operate on batteries with limited energy resources. Efficient power usage extends battery life.

Structure and Functionality of a CMOS Inverter

Basic Configuration

• A basic CMOS inverter consists of a PMOS device connected to a power supply (Vdd), with an NMOS device grounded at the bottom.

Input and Output Connections

• The gates of both PMOS and NMOS devices are tied together as input terminals while their drains connect to form the output terminal (Vout).

Load Capacitance

• A load capacitor (CL) is typically connected at the output terminal to manage load conditions effectively.

Conclusion: Significance of Study

Recap of Key Factors

• The analysis covers cost, robustness, performance, and energy efficiency—critical parameters influencing circuit design choices.

Application Across Circuits

Understanding CMOS Inverters and Their Layout

Introduction to CMOS Inverters

• The discussion begins with the application of a digital pulse at the input of a CMOS inverter, observing the output voltage (V_out).

• A distinction is made between schematic representations (symbolic view) and actual silicon layouts, emphasizing that the physical structure differs from theoretical drawings.

Layout of MOSFET Devices

• The layout for an inverter is introduced, showing how PMOS and NMOS transistors are arranged in practice.

• Detailed connections are described: NMOS source connected to ground, while PMOS source connects to V_dd. Both drains converge at the output terminal (V_out).

Pictorial Representation of Layout

• A pictorial view illustrates the layout design created using software, highlighting differences from schematic diagrams.

• Input nodes connect both PMOS and NMOS devices; PMOS is fabricated in an N-well while NMOS can be placed anywhere on the substrate.

Gate Connections and Metal Lines

• The poly-silicon gate connection runs from the input node to both devices, serving as their gate terminals.

• Drain connections for both transistors lead to a common output node via metal lines depicted in blue color within the layout.

Connecting Multiple Inverters

• The conversation shifts towards connecting multiple CMOS inverters together within a circuit system.

• A schematic representation shows two interconnected inverters where power supply rails (V_dd and GND) are shared among them for efficiency.

Design Considerations for Power Supply Rails

• Emphasis is placed on making V_dd and GND supply rails thick enough to handle current requirements across all circuits.

Understanding Inverter Layouts and SEOS Inverters

Overview of Inverter Design

• The thickness of supply rails (Vdd and GND) is significantly larger than that of the inverter components, ensuring adequate current delivery to devices.

• The first inverter's input terminal connects to an intermediate node, which links the output of the first inverter to the input of the second inverter.

• A common well is used for all PMOS devices in a layout, indicating shared resources among multiple transistors.

Detailed Layout Description

• The layout includes two PMOS (PMOS 1 and PMOS 2) and two NMOS (NMOS 1 and NMOS 2), demonstrating how they are interconnected within a single graphical representation.

• The layout serves as a visual guide for fabricating on silicon, illustrating how schematic designs translate into physical structures.

Functionality of SEOS Inverters

• When applying a static signal to an SEOS inverter, it operates differently based on whether V_in is high (Vdd) or low (ground).

• With V_in at Vdd, the PMOS turns off while NMOS acts as a resistor; this configuration allows discharging through RN at the output node.

Output Behavior Analysis

• If V_in is low (ground), NMOS turns off while PMOS behaves like a resistor. This results in current flowing from Vdd to output but not from output to ground due to NMOS being off.

• Key observations include that high and low output levels correspond directly with supply levels—either Vdd or ground—without intermediate values.

Characteristics of Ratioless Design

• An important feature of SEOS inverters is their ratioless design: logic levels do not depend on device sizes, leading to consistent outputs at either high or low states.

• The design ensures that regardless of input conditions, outputs remain firmly at either zero or one without fluctuating values.

Impedance Considerations

• High input impedance is crucial for SEOS inverters; it prevents current draw from external sources allowing multiple inverters to connect without affecting performance.

Understanding Static Power Dissipation in CMOS Inverters

Key Characteristics of CMOS Inverters

• Static Power Dissipation: There is no static power dissipation in the CMOS inverter when either PMOS or NMOS is off, as there is no direct current flowing from Vdd to ground during static conditions.

• Input Impedance: The input impedance of a CMOS inverter is very high, contributing to low power consumption when the signal remains static.

Voltage Transfer Characteristics (VTC) of a CMOS Inverter

• Basic Structure: The voltage transfer characteristic (VTC) can be visualized by plotting Vout against Vin, where Vout is high at low Vin due to PMOS being on and NMOS being off.

• Resistive Region: At low input voltages, the PMOS operates in the resistive region while NMOS remains off. This results in a high output voltage connected to Vdd.

• Transition Points: As Vin increases, NMOS turns on and enters saturation while PMOS stays resistive until both devices reach their respective saturation regions at midpoints of input transition.

Behavior During Input Signal Changes

• Region Shifts: With further increase in Vin, NMOS transitions into the resistive region as its drain-to-source voltage decreases. Conversely, PMOS enters saturation as its drain-to-source voltage increases.

• Typical VTC Shape: The typical shape of the VTC shows that at low input values, output is high; at high input values, output drops low with a gradual transition curve between these states.

Factors Affecting Voltage Transfer Characteristics

• Process Variation Impact: Variations during fabrication can lead to differences in performance between PMOS and NMOS devices affecting their strength and thus altering the VTC.

• Device Strength Comparison: The competition between PMOS and NMOS for controlling output depends on their relative strengths; variations can shift the balance leading to changes in VTC behavior.

Examples of Process Variation Effects

• Good vs Bad Devices: A good PMOS paired with a bad NMOS results in one type of shifted VTC; conversely, a good NMOS with a bad PMOS shifts it differently.

• Gate Oxide Thickness Influence: Good devices typically have smaller gate oxide thicknesses which contribute positively to their performance compared to poorer counterparts affected by process variations.

Device Performance and Variations in MOSFETs

Factors Influencing Device Performance

• The performance of a device is significantly affected by the gate oxide thickness; thinner gate oxides generally lead to higher current production, which is crucial for faster devices.

• Process variations can result in unintended changes to gate length (LG), where a smaller LG (5-10% less than targeted) can enhance device speed, making it act as a faster device rather than an optimal one.

• The driving capability of a device increases with larger width (WID); thus, both smaller LG and higher WID contribute to improved current driving capabilities.

• A lower threshold voltage (Vth) in MOSFETs also results in increased current flow, further enhancing the speed and performance of the device.

Impact on Circuit Performance