DDCA Ch6 - Part 17: RISC-V Immediate Encodings

Encodings of Immediates in RISC-V Instructions

In this section, the discussion revolves around the encodings of immediates in RISC-V instructions, focusing on different types of instructions and how immediates are handled within them.

Immediate Encoding in Different Instruction Types

• Load word and store word use 12-bit 2's complement numbers as constants or immediates directly available in the instruction.

• Different instruction types handle immediates distinctively:

• I or S Type Instruction: Takes a 12-bit immediate and sign extends it into upper bits.

• B Type Instruction: Utilizes an immediate with a zero in the least significant bit (bits 11-1) and sign extends the twelfth bit into upper positions.

• U Type Instruction: Contains zeros in the bottom 12 bits and places the immediate in the upper 20 bits.

• Understanding how different instruction types encode immediates is crucial for maintaining commonality between instructions. Key aspects include:

• The opcode always resides in bits 6 through 0 across all types.

• Register fields (rd, rs1, rs2) and funct3 consistently occupy fixed positions.

• Decoding an instruction involves identifying essential components like opcode, function fields, and sources. Immediates are relatively straightforward to create as they involve selecting specific bits without complex operations like accessing registers or memory.

Systematic Immediate Packing for Efficiency

• Hardware efficiently handles immediate encoding by systematically packing bits to ensure consistency across different instructions:

• Bits distribution for 'S' and 'B' types is strategically organized to maintain coherence.

• Consistency is maintained by placing specific bits at designated locations rather than scattering them randomly.