Organização de Computadores - Aula 06 - Conjunto de Instruções do MIPS

Introduction to MIPS Instruction Set Architecture

Overview of the Lesson

• The lesson focuses on the MIPS instruction set architecture, building upon previous discussions about computer organization and internal architecture.

• MIPS is a widely used educational example found in various textbooks, particularly noted for its relevance in embedded systems like routers and printers.

Characteristics of MIPS

• MIPS exemplifies RISC (Reduced Instruction Set Computer) architecture, which simplifies learning through straightforward instruction formats.

• The design of MIPS covers essential elements typical of modern instruction sets, making it an effective teaching tool.

Design Principles of MIPS

First Principle: Simplicity Favors Regularity

• Simplicity in instructions leads to easier decoding and simpler hardware implementation, enhancing processor performance.

• All arithmetic operations follow a consistent format with three operands: one destination and two source operands (e.g., a = b + c).

Second Principle: Smaller is Faster

• Accessing smaller registers is quicker than accessing larger main memory; fewer registers can lead to faster access times.

• MIPS utilizes 32 registers of 32 bits each, optimizing logical and arithmetic operations by minimizing access time.

Register Usage in MIPS

Types of Registers

• There are 32 registers numbered from 0 to 31; special names are assigned for ease of use in assembly language programming.

• Temporary ($T) and saved ($S) registers serve different purposes: temporary values may not need preservation across function calls while saved values must be restored after use.

Importance of Register Zero

Understanding MIPS Architecture and Memory Management

Importance of Zero in Programming

• The use of the constant zero is prevalent in programming, particularly in various disciplines. It enhances performance by avoiding memory access for this value.

• A register holding the value zero allows for efficient data movement between registers without a dedicated instruction for moving data in MIPS architecture.

Memory Addressing in MIPS

• MIPS memory is byte-addressable, meaning each address corresponds to a single byte. This flexibility allows access to bytes, half-words (16 bits), or full words (32 bits).

• Data must be aligned in memory; words should occupy complete lines from bit 0 to bit 31. Misalignment can lead to complications when accessing smaller data types.

• Instruction addresses must be multiples of four due to word alignment requirements, ensuring that instructions are fetched correctly from memory.

Endianness and Its Implications

• MIPS uses big-endian format where the most significant byte is stored at the lowest address. This affects how data is manipulated and accessed during assembly coding.

Example of Memory Access

• In an example involving C code (g = h + a), registers are mapped: S1 for g, S2 for h, and S3 as the base address for array a.

• To access an element like a, the base address needs to be offset by multiplying the index by four (the size of each word).

Optimizing Common Operations

• The design principle emphasizes making common cases faster, such as frequent increments or small additions often used in loops.

• Small constants can be directly embedded within instructions (up to 16 bits), reducing overhead from loading these values into registers repeatedly.

Instruction Formats in MIPS

• Instructions with immediate values allow operations without needing additional loads, streamlining processes like adding small constants directly within arithmetic operations.

Instruções do Tipo R e I no MIPS

Estrutura das Instruções do Tipo R

• Discussão sobre instruções com registradores, destacando a presença de um opcode que identifica a operação executada.

• Explicação da necessidade de 5 bits para os registradores RS e RT, totalizando 32 registradores disponíveis no MIPS.

• O campo "Shift amount" é utilizado em instruções de deslocamento, onde 5 bits são suficientes para representar deslocamentos até 32 posições.

• A função da instrução é identificada por um campo adicional, permitindo uma combinação com o opcode para reconhecer operações como soma e subtração.

• Exemplo prático de uma instrução de soma utilizando valores específicos para opcode e função, demonstrando como os registradores são mapeados.

Conversão e Execução das Instruções

• O processador converte as instruções em decimal para binário, empacotando-as em 32 bits para leitura na memória.

• Introdução às instruções do tipo I, que mantêm a regularidade no formato com campos semelhantes aos do tipo R.

Campos das Instruções do Tipo I

• As instruções aritméticas utilizam um campo imediato que representa constantes positivas ou negativas dentro de um intervalo específico (-2^15 a +2^15 - 1).

• Em operações de load, o valor imediato ajuda a compor endereços na memória ao ser somado ao endereço base contido no registrador RS.

• Necessidade de extensão de sinal ao trabalhar com endereços, garantindo que os dados sejam manipulados corretamente em 32 bits.

Tipos de Instrução e Desvios

• Importância da faixa ampla de endereços na memória versus a regularidade dos formatos das instruções; compromisso entre flexibilidade e estrutura.

• As instruções de desvio (branching), que comparam dois registradores (RS e RT), determinam se devem desviar baseado nos resultados dessas comparações.

Conclusão sobre Instruções J

Understanding Unconditional Jumps in Instruction Sets

Overview of Unconditional Jumps

• Unconditional jumps are instructions that redirect execution flow regardless of conditions, specifically using jump or jump and link instructions.

• These instructions change the program counter to a different address, which is crucial for control flow in programming.

Addressing Mechanism

• The addressing scheme involves 32-bit addresses; however, only 26 bits are utilized in certain contexts, necessitating a design decision by architects.

• A new addressing module combines the most significant bits from the instruction counter with the 26-bit address to form a complete address.