L3 2 Funcionamiento del procesador: ejecución de instrucciones.

Name: L3 2 Funcionamiento del procesador: ejecución de instrucciones.
Uploaded: 2014-05-16T23:48:03.000Z
Duration: 1 h 4 min 47 s

Process of Instruction Execution

Introduction to the Basic Computer Model

The presentation focuses on the execution process of instructions using a basic computer model called "computador didáctico elemental" which simplifies understanding computer operations.

This model features a regular instruction format with only 16 instructions, making it suitable for educational purposes and foundational learning in computing.

Overview of Code2

The textbook accompanying the course provides a comprehensive design description of Code2, enhancing the learning experience with practical applications.

An emulator and assembler related to Code2 are available as free software, allowing users to experiment and learn effectively. Information can also be found on Wikipedia under "code2."

Structure of Code2

The structure includes 16 general-purpose registers, an arithmetic logic unit (ALU), a temporary register, and an address register connected to the system's address bus for memory access.

Control unit components include a program counter, instruction register, stack pointer, and clock among others essential for operation management.

Initial Program Execution Steps

To execute a program, the starting address must be loaded into the program counter via a jump instruction; in this case, it's set to address 1A.

The first instruction (73C) is then fetched from memory into the distribution register by directing the address register to read from memory based on the program counter's value.

Instruction Fetching Process

After fetching data from memory (73D), it is loaded into an internal data register within the processor before being transferred to the instruction register (IR). This step updates IR with 73C as it prepares for execution.

The program counter is incremented by one after loading IR since it always holds the next instruction's address that needs execution. This marks completion of initial steps in executing a program.

Phases of Instruction Execution

Once captured in IR, control circuits interpret this information during what’s known as the execution phase where control signals are generated for both internal and external operations necessary for executing that instruction.

Each machine cycle involves capturing an instruction followed by its execution; this cycle repeats continuously throughout processing tasks ensuring efficient operation management within Code2 architecture.

Key Insights on Instruction Handling

In Code2's architecture, each instruction occupies one memory position unlike some Intel architectures where multiple positions may be required per instruction leading to more complex fetching processes during execution phases.

Microoperations and Instruction Execution

Understanding Microoperations

Microoperations are fundamental operations performed by a computer, such as loading registers, incrementing program counters, and reading/writing memory.

These microoperations are synchronized with the clock and typically consume one or more clock cycles; most consume only one cycle while read/write operations may take several.

Some microoperations can occur simultaneously in different processor areas, while others cannot due to their dependencies.

Phases of Instruction Execution

The execution of a machine instruction involves a specific sequence of microoperations that follow a predetermined order across multiple clock cycles.

The process begins with the "fetch" phase where necessary microoperations are executed before moving to the "execution" phase based on the operation code (opcode).

Example of Instruction Timing

An example is provided using a 16-bit word computer (Code 2), illustrating how instructions are fetched from memory and executed.

For instance, an instruction at memory position C039 (binary 0700) transfers data from memory to register R7. The address Rd contains the location of this data.

Detailed Execution Steps

Upon executing instruction 0700, various registers like the program counter (PC), instruction register (IR), address register (AR), data register (DR), and R7 undergo changes.

After fetching the instruction, PC points to the next instruction's address while IR holds the current instruction. Rd indicates where to find data for R7.

Reading Data from Memory

To execute this instruction, first load AR with Rd's content which specifies where in memory to read from.

Once AR has the correct address, it appears on the address bus allowing access to that specific memory location for reading data into DR.

Finalizing Execution

The control unit then directs loading DR's value into R7 after reading from memory. This completes executing the instruction involving multiple microoperations: transferring Rd to AR, reading from memory into DR, and finally moving DR’s content into R7.

Execution of Instructions in a Processor

Overview of Instruction Execution

The program counter is in the instruction execution phase, where data from memory is loaded into register R.

Data read from memory (54C2) is transferred to register R7, completing the microoperation table for instruction timing.

The general operation of loading a register with memory content involves specific microoperations that can be analyzed for all instructions.

Instruction Fetching and Execution Cycles

Instruction fetching is common across all instructions, while execution phases are specific to each opcode.

Different instructions consume varying clock cycles; for example, loading takes three cycles, while jumps may take one or four depending on complexity.

Execution time can be calculated by multiplying cycle count by period or using frequency; higher clock frequencies result in shorter execution times.

Control Instructions and Their Functions

Control instructions allow altering the sequential execution order of programs by jumping to specified memory addresses.

After executing a jump instruction, subsequent instructions are executed starting from the new address set by the jump.

Types of Control Instructions

There are various types of control instructions: unconditional/conditional jumps (JUM), calls (CALL), and returns (RET).

Conditional jumps only occur if certain conditions are met based on status flags like zero or overflow indicators.

Jump Execution Process

When executing a jump, the processor updates the program counter with the target address stored in Rd.

For instance, if Rd contains 10A3 during a jump at address 107A, PC will update to 10A3 instead of continuing sequentially.

Example of Jump Instruction

An example illustrates how after executing a branch instruction at 107A, PC changes to 10A3 based on Rd's value.

This automatic change allows seamless continuation until another jump instruction alters flow again.

Understanding Subroutines and Their Execution

Introduction to Subroutines

A subroutine, also known as a procedure or routine, is executed after a call instruction. The term "subroutine" is preferred for its classical usage.

Upon completion of a subroutine, control returns to the calling program using a return instruction.

Nesting of Subroutines

A subroutine can invoke other subroutines, leading to nesting. For example, if a program at address 107A calls a subroutine at address 1A3.

If this first subroutine calls another one at address 6FB, it continues executing until it reaches the end of that second subroutine.

Return Mechanism

Each time a return instruction is executed in a subroutine, control must go back to the exact point where the call was made (e.g., from AB36 back to 6FC).

It’s crucial to store return addresses (like 107B, 6FC, and AB36) temporarily during execution for proper control flow.

Difference Between Jump and Call Instructions

Unlike jump instructions that do not require returning control, call instructions necessitate storing return addresses for later retrieval.

These return addresses are stored in memory temporarily during execution and retrieved in reverse order when needed.

Stack Memory Concept

A stack memory system allows information retrieval in reverse order (Last In First Out - LIFO). This structure is essential for managing nested calls effectively.

During calls to subroutines, the program counter's content must be saved onto the stack before changing its value to point to the new subroutine's start address.

Implementation of Stack Memory

Return instructions are simpler; they involve extracting the top address from the stack and placing it back into the program counter.

High-speed computers may use hardware stacks integrated into processors; however, most systems simulate stacks using main memory (software stacks).

Stack Pointer Functionality

The processor maintains a specific register called "stack pointer" which tracks where the last return address was stored in memory.

When new calls occur, subsequent return addresses are pushed onto this stack area reserved within RAM.

Subroutine Call and Return Process

Understanding Stack Pointer Operations

The stack pointer (SP) holds the address of the stack header, which is crucial for managing subroutine calls. This value is repeated in the figure for clarity.

When calling a subroutine, the return address must be stored at the stack header. To do this, SP needs to be decremented by one since lower memory addresses are at the top of the figure.

The operation SP - 1 updates SP to point to where the new return address will be stored. This ensures that we have an accurate location for writing back data.

To write to memory, we transfer SP's content to an address register (AR). We also need to store the program counter (PC) value into a data register (DR), safeguarding it during execution.

With AR holding the target memory address and DR containing data, control can issue a write command. This writes DR's content into memory at AR's specified position.

Executing Subroutine Calls

For jumping to a subroutine, we must load PC with a new jump address after saving its current value in memory. This involves transferring DR’s content back into PC.

Returning from Subroutines

The return process begins by reading from SP, which contains the return address needed for PC. First, we move SP's value into AR.

A read command fetches data from memory using AR; this data is then transferred via the data bus into DR.

Finally, we update PC with DR’s content to complete the return process. After extracting this return address, SP must increment by one as it now points to a new stack header position.

Summary of Instruction Execution Phases

Instruction execution consists of two phases: fetching and executing. Fetching brings instructions into the instruction register for processing.

During execution, control unit interprets instructions and generates control signals that trigger corresponding microoperations necessary for instruction completion.

Each instruction comprises multiple microoperations executed in a specific sequence tailored to achieve desired outcomes effectively.